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Register-transfer level
Results: 34

#	Item
11	Enhanced Reliability Design Automation Methodology considering the Generation of Parallel CRC Modules based on arbitrary CRC Polynomials and unlimited Data-Word Widths Timo Brenningmeyer University of Applied Sciences Os Add to Reading List Source URL: www.ecs.hs-osnabrueck.de Language: English - Date: 2012-04-13 13:29:50 Hardware description language Cyclic redundancy check Verilog Logic synthesis High-level synthesis CRC Register-transfer level Checksum Cksum Electronic engineering Electronic design automation Digital electronics
12	Datasheet Design Compiler Graphical Create a Better Starting Point for Faster Physical Implementation Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:53 Design closure Register-transfer level Compiler Floorplan Placement Place and route Static single assignment form Program optimization EDA database Electronic engineering Electronic design automation Physical design
13	Datasheet DC Explorer Early RTL Exploration Accelerates Design Schedules Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:50 Design closure Register-transfer level Design flow Clock gating Integrated circuit design Electronic engineering Electronic design automation Physical design
14	Datasheet DC Ultra Concurrent Timing, Area, Power and Test Optimization Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-19 18:15:41 Logic synthesis Physical design High-level synthesis Register-transfer level Placement Quality of results Multi-core processor Synopsys Retiming Electronic engineering Electronic design automation Electronics
15	Datasheet VCS Xprop Increasing the Efficiency of X-related Simulation and Debug Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:41:23 Hardware verification languages Digital electronics Verilog VHDL Logic simulation Register-transfer level SystemC Logic synthesis Synopsys Electronic engineering Electronic design automation Hardware description languages
16	UW-System English, Mathematics, and Foreign Language Placement Test ALL NEW STUDENTS (freshman and transfer students) entering UW-Platteville MUST take the UW-System English and Mathematics Placement Test before register Add to Reading List Source URL: www.uwplatt.edu Language: English - Date: 2014-12-08 12:01:50 College Level Examination Program ACT Advanced Placement Education Standardized tests Educational programs
17	Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs Joachim Pistorius, Mike Hutton Altera Corp. 101 Innovation Drive San Jose, CA 95134 {jpistori,mhutton}@altera.com Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-04-20 22:36:42 Logic synthesis Physical design Register-transfer level Altera Quartus Place and route Application-specific integrated circuit Integrated circuit design Digital electronics Semiconductor intellectual property core Electronic engineering Electronic design automation Field-programmable gate array
18	Calypto Announces New President and CEO Sanjiv Kaul SAN JOSE, Calif., – February 4, 2013 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level ( Add to Reading List Source URL: calypto.com Language: English - Date: 2013-03-21 16:28:44 Synopsys Mentor Graphics Electronic system-level design and verification SystemVerilog Catapult C Electronic engineering Electronic design automation High-level synthesis
19	17th LUXEMBOURG EURO MEET 30th January – 1st February 2015 Online registration procedure for the Luxembourg Euro Meet This document explains how to register for the 17th Luxembourg Euro Meet via the Add to Reading List Source URL: app.euromeet.lu Language: English - Date: 2014-11-07 00:52:04 International Bank Account Number ISO Euro Wire transfer Financial system .lu Business European Union Financial regulation Identifiers Country code top-level domains
20	CSEE W4823x Prof. Steven Nowick CSEE* W4823x Course Information Handout 1 Add to Reading List Source URL: www.cs.columbia.edu Language: English - Date: 2012-09-05 12:10:27 Digital electronics Computer engineering Algorithmic State Machine VHDL Register-transfer level Logic synthesis Asynchronous circuit Power optimization Integrated circuit design Electronic engineering Electronic design automation Electronic design